1. Field of the Invention
This invention relates to a digital signal processor(DSP) for processing various digital signals depending upon any programs.
2. Description of the Prior Art
Nowadays several digital signal processing algorithms are implemented with a hardwired device or a programmable DSP. Such digital signal processing algorithms include complex arithmetic formulas such as fast fourier transform(FFT). For example, xe2x80x9cAC-3xe2x80x9d suggested as an audio compression and reconstruction algorithm by Dolby Co. Ltd. uses IFFT having a block length of xe2x80x9c64xe2x80x9d when being intended to improve a resolution of a signal on the time axis; while it uses IFFT having a block length of xe2x80x9c128xe2x80x9d when being intended to improve a resolution of a signal on the frequency axis. As shown in FIG. 1, such a reverse transform method of the AC-3 algorithm includes a pre-IFFT, a complex IFFT and a post-IFFT that are successively performed after coefficients to be used in the transform are defined. Also, a windowing arithmetic and an overlap and add arithmetic followed by the post-IFFT are sequentially performed. FIG. 2 shows an embodiment of a radix-2 FET algorithm having a block length of xe2x80x9c8xe2x80x9d. In the radix-2 algorithm, a butterfly structure arithmetic as shown in FIG. 3 is used regularly. The butterfly structure arithmetic as shown in FIG. 3 can be expressed as the following equations:
Xout=xin+yinxc2x7WkN
Yout=xinxe2x88x92yinxc2x7WkN. (WkN=exe2x88x922xcfx80k/N)
Re(Xout)=Re(Xin)+Re(yin)cos(xe2x88x922xcfx80k/N)xe2x88x92Im(yin)sin(xe2x88x922xcfx80k/N)
Im(Xout)=Im(Xin)+Im(yin)cos(xe2x88x922xcfx80k/N)+Re(yin)sin(xe2x88x922xcfx80k/N)
Re(Yout)=Re(Xin)xe2x88x92Re(yin)cos(xe2x88x922xcfx80k/N)+Im(yin)sin(xe2x88x922xcfx80k/N)
Im(Yout)=Im(Xin)xe2x88x92Im(yin)cos(xe2x88x922xcfx80k/N)xe2x88x92Re(yin)sin(xe2x88x922xcfx80k/N)xe2x80x83xe2x80x83(1)
wherein Re(x) and Im(x) represent a real number part and an imaginary number part, respectively. Also, in the radix-2 algorithm of FIG. 2, butterfly arithmetical groups are multiplexed. The butterfly arithmetical group is obtained by multiplexing the butterfly structure arithmetics, as shown FIG. 4. Further, the radix-2 algorithm with the multiplexed butterfly arithmetical groups is provided to the FFT, as a butterfly arithmetical stage. Accordingly, the FFT consists of the plurality of the butterfly arithmetical stages. In order to operate the FFT, conventional DSPs repeatedly perform steps as shown in the flowchart of FIG. 5.
In order to perform all the operations which are from the simple four arithmetical operations to the FFT including the butterfly structure operation, in the DSP, how fast can each command word be processed is regarded as an important factor. In other words, a period of the command word in the DSP must be shortened and command words as much as possible must be processed in parallel so as to perform a high speed process of the command word. The command word parallel processing capability has required from the time when the DSP was used for the video/audio decoder, and which can be attained by carrying out a plurality of commands in parallel differently from the previous sequential command execution. Accordingly, the recent DSPs has been provided with special command words permitting the parallel process. For example, the ADSP in ADSP21020 model of Analog Device Co. has special command words that allow a number of complex arithmetic equations to be processed within only several clock periods like the butterfly operation for the FET arithmetic. To this end, the ADS21020 is provided with a register file consisting of at least 12 registers related to the operation. Further, the DSP in ZR38000 model of Zoran Co. can process a number of complex arithmetic equations within several clock periods. To this end, the ZR38000 has a register file consisting of 8 registers and a structure which is capable of performing a multiplication and a resultant addition and subtraction at a time within one clock period.
Accordingly, it is an object of the present invention to provide a digital signal processor and a digital signal processing method that are capable of rapidly operating a number of complex arithmetic formulae as such FFT.
Further object of the present invention is to provide a fast fourier transform control method that is adaptable for rapidly performing a fast fourier transform procedure.
In order to achieve these and other objects of the invention, a digital signal processing method according to an aspect of the present invention comprises steps of: operating data from first input line and data from second input line by means of first operating means; operating data from any one of the first and second input lines and data from the first operating means by means of second operating means; and operating the data from any one of the first and second input lines and the data from the first operating means by means of third operating means.
A digital signal processing method according to another aspect of the present invention comprises steps of: operating data from first input line and data from second input line by means of first operating means; operating data from the first operating means and data from any one of first feedback line and the first and second input lines by means of second operating means, the first feedback line be connected to first register for storing the data from the second operating means; and operating data from the first operating means and data from any one of second feedback line and the first and second input lines by means of third operating means, the second feedback line being connected to the register for storing the data from the third operating means.
A digital signal processing method according to still another aspect of the present invention comprises steps of: operating data from first input line and data from second input line by means of first operating means; operating data from the first operating means and data from any one of first and second feedback line and the first and second input lines by means of second operating means; and operating data from the first operating means and data from any one of the first and second feedback line and the first and second input lines by means of third operating means, the first feedback line being connected to first register for storing the data from the second operating means, the second feedback line being connected to second register for storing the data from the third operating means.
A digital signal processor according to still another aspect of the present invention includes: first and second input means for receiving N-bit data, respectively; first operating means for operating the data from the first input means and the data from the second input means; second operating means for operating the data from any one of the first and second input means and data from the first operating means; and third operating means for operating the data from any one of the first and second input means and the data from the first operating means.
A digital signal processor according to still another aspect of the present invention includes: first and second input means for receiving N-bit data, respectively; first operating means for operating the data from the first input means and the data from the second input means; second operating means for operating data from the first operating means and data from any one of first feedback line and the first and second input means; third operating means for operating the data from the first operating means and data from any one of second feedback line and the first and second input means; first register being connected to the first feedback line for temporarily storing the data from the second operating means; and second register being connected to the second feedback line for temporarily storing the data from the third operating means.
A digital signal processor according to still another aspect of the present invention includes: first and second input means for receiving N-bit data, respectively; first operating means for operating the data from the first input means and the data from the second input means; second operating means for operating data from the first operating means and data from any one of first and second feedback lines and the first and second input means; third operating means for operating the data from the first operating means and data from any one of the first and second feedback lines and the first and second input means; first register being connected to the first feedback line for temporarily storing the data from the second operating means; and second register being connected to the second feedback line for temporarily storing the data from the third operating means.
A digital signal processor according to still another aspect of the present invention includes: first and second input means for receiving N-bit data, respectively; first operating means for operating the data from the first input means and the data from the second input means; scaling means for scaling up the data from the first and second input means and the first operating means; second operating means for operating data from the first operating means and the data from any one of the scaling means and the first and second input means; and third operating means for operating the data from the first operating means and the data from any one of the scaling means and the first and second input means.
A digital signal processor according to still another aspect of the present invention includes: first and second input means for receiving N-bit data, respectively; first operating means for operating the data from the first input means and the data from the second input means; second operating means for operating data from the first operating means and data from any one of first feedback line and the first and second input means; third operating means for operating the data from the first operating means and data from any one of second feedback line and the first and second input means; scaling means for scaling up the data from any one of the first and second feedback line and the first and second input means; first register being connected to the first feedback line for temporarily storing the data from the second operating means and the scaling means; and second register being connected to the second feedback line for temporarily storing the data from the third operating means and the scaling means.
A digital signal processor according to still another aspect of the present invention includes: first and second input means for receiving N-bit data, respectively; first operating means for operating the data from the first input means and the data from the second input means; second operating means for operating data from the first operating means and data from any one of first and second feedback lines and the first and second input means; third operating means for operating the data from the first operating means and data from any one of the first and second feedback lines and the first and second input means; scaling means for scaling up the data from any one of the first and second feedback line and the first and second input means; first register being connected to the first feedback line for temporarily storing the data from the second operating means and the scaling means; and second register being connected to the second feedback line for temporarily storing the data from the third operating means and the scaling means.
A fast fourier transform control method according to still another aspect of the present invention comprises steps of: identifying value of phase angle included in complex arithmetic equation of the fast fourier transform; selecting any one among at least two procedure control modes on the basis of identified resultant; and performing the fast fourier transform in accordance with selected procedure control mode.